An FPGA‐based JPEG preprocessing accelerator for image classification

The FPGA-based image classification accelerator has achieved success in many practical applications. However, most accelerators focus on solving the problem of convolution computation efficiency. End-to-end involves non-convolutional operations, which can also become performance bottlenecks. Therefore, authors propose an JPEG preprocessing accelerator, accelerate non-convolution operations before feature extraction. To improve throughput and energy efficiency, four hardware structures are adopted design: 1) adaptive block; 2) fast IDCT; 3) block buffer; 4) self-location. proposed design is evaluated Xilinx XCZU7EV. compare it with optimized implementation CPU GPU, efficiency improved by 23.07 times 4.21 times, respectively. 2.52 better than implementation. And demonstrate its practicality through a case study classification. These experimental results superior terms